Generally, a decoupling capacitor is connected between a power supply line and ground with the aim of avoiding superposition of voltage fluctuations of a direct-current power supply and noise in an electronic circuit.
In such a decoupling application, low equivalent series resistance (ESR) is demanded, and in particular, from the viewpoint of eliminating noise in a high-frequency range of over 100 MHz, for example, very low equivalent series inductance (ESL) is demanded.
An effective way of reducing ESR and ESL is to arrange terminals of different polarities (first surface electrodes and second surface electrodes) in a planar grid-like pattern, as described in Patent Document 1 for example. As a result, the number of current paths having a parallel relationship is increased, and ESR is consequently reduced. In addition, the directions of currents that flow through upper and lower electrodes sandwiching a dielectric layer therebetween and the directions of currents that flow through conductors that extend in the stacking direction are respectively opposite to each other, and as a result, generation of magnetic fields is suppressed. Therefore, ESL is reduced. Furthermore, the overall current path is shortened, and consequently, ESR and ESL are reduced.    Patent Document 1: International Publication No. 2007/046173